Semiconductor chips assembled in advanced packages may be subject to significant mechanical pressure, mechanical stress, humidity, and/or temperature cycling during manufacturing and testing as well as in the end user environment. This may result in chip failures cause by, e.g., cracks and/or delamination in the interconnect levels, the device/transistor level, and/or the chip substrate itself. Chips that use advanced technology nodes, such as those that include Cu/low k interconnects, are even more prone to failure due to the inherent mechanical weakness of dense and porous low k materials.
Some materials such as low k dielectrics are particularly sensitive to the intrusion and diffusion of moisture such as water. Such moisture intrusion may increase the k-value (dielectric constant) due to the high polarity of water molecules, and may result in increasing RC-delays, signal degradation, increasing interconnect capacitive load, parasitic power loss, and/or interconnect corrosion.
For some chips, such as power chips, temperature variations can result in significant warpage of the chips inside their packages, such as by changing from a convex deformation at −55° C. to a concave deformation at +150° C. with center-edge differences of up to approximately 2 μm. This warpage can lead to large intrinsic stress and strain within the chips, which in turn can result in early failure or degradation of the chip.
It has already been proposed that piezo-electric resistors may be embedded in chip substrates to measure stress levels. However, these would likely have only marginal sensitivity to the localized chip/package interaction stresses in the interconnect or back-end-of-line (BEOL) stack (such as in one of the weaker Cu/low k levels). Moreover, such resistors would likely not detect other factors such as mechanical pressure or humidity.